As memory cells used in random access memories (RAM), 1T1C (one transistor-one capacitor)-type memory cells and 2T-type or 3T-type memory cells are known. These memory cells store data by charging and discharging retention nodes with write transistors.
It has been proposed that a transistor whose channel formation region is formed using an oxide semiconductor (hereinafter also referred to as an oxide semiconductor transistor or an OS transistor) is employed as a write transistor in these memory cells. For example, Patent Document 1 discloses a memory cell that can retain data even in the situation in which power is not supplied, by including the OS transistor as a write transistor. A memory including an OS transistor can be used as a nonvolatile memory.
As an example of a nonvolatile memory, a flash memory is known. There is an upper limit of the cycling capability of the flash memory, which is generally about 1×105 times. As the cycling capability of the flash memory increases, the rate of error occurrence at the time of access increases; thus, the cycling capability of the flash memory greatly affects the lifetime of the flash memory. In order to extend the lifetime of the flash memory, an error check and correct (ECC) circuit is widely used in the flash memory to correct data of a failure bit (for example, see Patent Document 2). As the number of bits in one block of the flash memory becomes larger, the number of redundant bits needed to correct an error becomes relatively smaller; thus, the utilization efficiency of a storage region increases. In general, a memory is accessed in blocks of several tens of bits to several tens of thousands of bits to perform ECC.